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Integrated Circuit Systems, Inc.
ICS1523
High-Performance Programmable Line-Locked Clock Generator
General Description
The ICS1523 is a low-cost but very high-performance frequency generator for line-locked and genlocked highresolution video applications. Using ICSs advanced low-voltage CMOS mixed-mode technology, the ICS1523 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA. The ICS1523 offers pixel clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase Adjust circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-bus serial interface and is available in a 24-pin wide small-outline integrated circuit (SOIC) package.
Features
Pixel clock frequencies up to 250 MHz Very low jitter Dynamic Phase Adjust (DPA) for clock outputs Balanced PECL differential outputs Single-ended SSTL_3 clock outputs Double-buffered PLL/DPA control registers Independent software reset for PLL/DPA External or internal loop filter selection Uses 3.3Vdc. Inputs are 5V-tolerant. I2C-bus serial interface can run at either low speed (100 kHz) or high speed (400 kHz). Lock detection 24-pin 300-mil SOIC package
Applications
LCD monitors and video projectors Genlocking multiple video subsystems Frequency synthesis
Block Diagram
Pin Configuration
24-Pin SOIC
I C-bus is a trademark of Philips Corporation. Dynamic Phase Adjust is a trademark of Integrated Circuit Systems, Inc.
ICS1523 Rev S 5/21/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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ICS1523
Document Revision History
Rev P (First Release) Pin Descriptions changed to add type column. (pg 3) Added SDA and AC Input Characteristics. (pg 18) Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19) Timing diagram changes to reference t0 to REF and notes on test conditions added (pg 22) Lock Renamed Lock/Ref (Throughout). General cleanup for readability. Rev Q Added typical external loop filter values. (pg 17) Added section on power supply considerations and SSTL_3 outputs. (pg 18) Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20) Correct depiction of timing diagram and added typical transition timing. (pg 23) Added Document Revision History. (pg 25) Change to descriptions for pins 20 to 23. (pg 3) Change to description for Reg 0h bits 0 and 1, added table. (pg 6) Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6) Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7. Change to Software Programming Flow diagram. (pg 13). Added under Absolute Maximum Ratings ESD ratings and warning. (pg 19) Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added a new page. (pg 19) Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19) Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20)
Rev R
Rev S
Moved Revision History from last page of data sheet to second page. (pg 2) In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19) Changed various cross-references within Layout Guidelines. (pg 19)
2
ICS1523
Overview
The ICS1523 addresses stringent graphics system line-locked and genlocked applications and provides the clock signals required by high-performance video analog-to-digital converters. Included are a phase-locked loop (PLL) with a 500-MHz voltage controlled oscillator (VCO), a Dynamic Phase Adjust to provide a user-programmed pixel clock delay, the means for deMUXing multiplexed ADCs, and both balanced-programmable (PECL) and single-ended (SSTL_3) high-speed clock outputs. Phase-Locked Loop The phase-locked loop is optimized for line-locked applications, for which the inputs are horizontal sync signals. A high-performance Schmitt trigger preconditions the HSYNC input, whose pulses can be degraded if they are from a remote source. This preconditioned HSYNC signal is provided as a clean reference signal with a short transition time. (In contrast, the signal that a typical PC graphics card provides has a transition time of tens of nanoseconds.) A second high-frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection allows the loop to operate from a local source and is also useful for evaluating intrinsic jitter. A 12-bit programmable feedback divider completes the loop. Designers can substitute an external divider. Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, aligned to the edge of the pixel clock. Automatic Power-On Reset Detection The ICS1523 has automatic power-on reset detection circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required. Dynamic Phase Adjust The Dynamic Phase Adjust allows addition of a programmable delay to the pixel clock output, relative to the recovered HSYNC signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one pixel clock period is selectable in the following increments: 1/64 period for pixel clock rates to 40 MHz 1/32 period for pixel clock rates to 80 MHz 1/16 period for pixel clock rates to 160 MHz Output Drivers and Logic Inputs The ICS1523 utilizes low-voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudoECL) outputs, operating at 3.3-V supply voltage. The LVTTL inputs are 5 V-tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated. I2C-bus Serial Interface The ICS1523 utilizes the industry-standard I2C-bus serial interface. The interface uses 12 registers: one write-only, eight read/write, and three read-only. Two ICS1523 devices can be addressed, according to the state of the I2CADR pin. When the pin is low, the read address is 4Dh, and the write address is 4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh. The I2C-bus serial interface can run at either low speed (100 kHz) or high speed (400 kHz) and provides 5V-tolerant input.
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ICS1523
Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P I N NA M E VDDD VSSD S DA SCL PDEN EXTFB HSYNC EXTFIL XFILRET V D DA VSSA OSC I2 CADR LOCK/REF (SSTL) FUNC (SSTL) CLK/2 (SSTL) CLK (SSTL) VDDQ VSSQ CLK- (PECL) CLK+ (PECL) CLK/2- (PECL) CLK/2+ (PECL) IREF TYPE PWR PWR IN/OUT IN IN IN IN IN IN PWR PWR IN IN OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT IN DESCRIPTION Digital supply Digital ground Serial data Serial clock PFD enable External feedback in Horizontal sync External filter External filter return Analog supply Analog ground Oscillator I2 C address Lock indicator/reference Function output P i xe l c l o c k / 2 o u t P i xe l c l o c k o u t Output driver supply Output driver ground P i xe l c l o c k o u t P i xe l c l o c k o u t P i xe l c l o c k / 2 o u t P i xe l c l o c k / 2 o u t Reference current I2 C-bus1 I2 C-bus1 S u s p e n d s c h a rg e p u m p 1 External divider input to P F D 1 Clock input to PLL1 External PLL loop filter External PLL loop filter return 3.3V for analog circuitry Ground for analog circuitry Input from crystal oscillator package1 , Chip I C address select Low = 4Dh read, 4Ch write High = 4Fh read, 4Eh write Displays PLL or DPA lock or REF input SSTL_3 selectable HSYNC output SSTL_3 driver to ADC deMUX input SSTL_3 driver to ADC 3.3V to output drivers Ground for output drivers Inverted PECL driver to ADC. Open drain. PECL driver to ADC. Open drain. Inverted PECL driver to ADC deMUX input. Open drain. PECL driver to ADC deMUX input. Open drain. Reference current for PECL outputs
2 2
COMMENTS 3.3V to digital sections
Notes:
1. These LVTTL inputs are 5 V-tolerant. 2. Connect to ground if unused.
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ICS1523
Block Diagram
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ICS1523
I2C Register Map Summary
Register Index 0h Name Input Control Access R/W Bit Name PDen PD_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnDLS 1h Loop Control R/W* PFD0-2 Reserved PSD0-1 Reserved 2h 3h FdBk Div 0 FdBk Div 1 R/W* R/W* FBD0-7 FBD8-11 Reserved 4h DPA Offset R/W DPA_OS0-5 Reserved Fil_Sel 5h DPA Control R / W ** DPA_Res0-1 Metal_Rev 6h Output Enables R/W OE_Pck OE_Tck OE_P2 OE_T2 OE_F Ck2_Inv Out_Scl 7h Osc_Div R/W Osc_Div 0-6 In-Sel 8h Reset Write DPA PLL 10h 11h 12h Chip Ver Chip Rev Rd_Reg Read Read Read Chip Ver Chip Rev DPA_Lock PLL_Lock Reserved Bit # 0 1 2 3 4 5 6 7 0-2 3 4-5 6-7 0-7 0-3 4-7 0-5 6 7 0-1 2-7 0 1 2 3 4 5 6-7 0-6 7 0-3 4-7 0-7 0-7 0 1 2-7 Reset Value 1 0 0 0 0 0 1 0 0 0 0 0 FF F 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 x x 17 01 N/A N/A 0 Description Phase Detector Enable (0=External Enable, 1=Always Enabled) Phase Detector Enable Polarity (0=Not Inverted, 1=Inverted) External Reference Polarity (0=Positive Edge, 1=Negative Edge) External Feedback Polarity (0=Positive Edge, 1=Negative Edge) External Feedback Select (0=Internal Feedback, 1=External) Function Out Select (0=Recovered HSYNC, 1=Input HSYNC) Enable PLL Lock/Ref Status Output (0=Disable 1=Enable) Enable DPA Lock/Ref Status Output (0=Disable 1=Enable) Phase Detector Gain Reserved Post-Scaler Divider (0 = /2, 1 = /4, 2 = /8, 3 = /16) Reserved PLL FeedBack Divider LSBs (bits 0-7) * PLL Feedback Divider MSBs (bits 8-11) * Reserved Dynamic Phase Aligner Offset Reserved Loop Filter Select (0=External, 1=Internal) DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64) Metal Mask Revision Number Output Enable for PECL PCLK Outputs ( 0=High Z, 1=Enabled) Output Enable for STTL_3 CLK Output ( 0=High Z, 1=Enabled) Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled) Output Enable for STTL_3 CLK/2 Output ( 0=High Z, 1=Enabled) Output Enable for STTL_3 FUNC Output ( 0=High Z, 1=Enabled) CLK/2 Invert (0=Not Inverted, 1= Inverted) SSTL Clock Scaler (0 = /1, 1 = /2, 2 = /4, 3 = /8) Osc Divider modulus Input Select (0=HSYNC Input, 1=Osc Divider) Writing xAh resets DPA and loads working register 5 Writing 5xh resets PLL and loads working registers 1-3 Chip Version 23 Dec (17 Hex) as in 1523 Initial value 01h. Value Increments with each all-layer change. DPA Lock Status (0=Unlocked, 1=Locked) PLL Lock Status (0=Unlocked, 1=Locked) Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset. ** Identifies double-buffered register. Working registers are loaded during software DPA reset.
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ICS1523
Detailed Register Description
Name: Register: Index:
PDen PD_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnDLS
Input Control 0h Read / Write
0 1 2 3 4 5 6 7 1 0 0 0 0 0 1 0 Phase/Frequency Detector Enable Phase/Frequency Detector Enable Polarity Phase/Frequency Detector External Reference Polarity External Reference Feedback Polarity External Feedback Select Function Output Select Enable PLL Lock Status Output on LOCK/REF pin Enable DPA Lock Status Output on LOCK/REF pin
Bit Name Bit # Reset Value Description
Bit
0 1 2
Name
PDen PD_Pol Ref_Pol
Description
Phase/Frequency Detector Enable Phase/Frequency Detector Enable Polarity
PDen 0 X 1 PD_Pol 0 1 0 P h a s e / F r e q u e n cy D e t e c t o r Is Enabled When: PDEN= 1 A lwa y s ( D e fa u l t ) PDEN = 0
Phase/Frequency Detector External Reference Polarity Edge of input signal on which Phase Detector triggers. 0 = Rising Edge (default) 1 = Falling Edge External Reference Feedback Polarity Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default) 1 = Negative Edge
3
Fbk_Pol
Table continues on next ppage
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ICS1523
Name: Input Control Register: 0 h
Bit
4
Name
Fbk_Sel
Description
External Feedback Select 0 = Internal Feedback (default) 1 = External Feedback Function Output Select Selects re-clocked output to FUNC (pin 15). 0 = Recovered HSYNC (default). Re-generated HSYNC output. 1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7). Enable PLL Lock Status Output on LOCK/REF pin Enable DPA Lock Status Output on LOCK/REF pin Bits 6,7 enable multiple functions at LOCK/REF, (pin 14)
EnPLS EnDLS IN_SEL LOCK/REF(14) 0 0 N/A 0 0 1 N/A 1 if DPA locked, 0 otherwise 1 0 N / A 1 i f P L L l o c ke d , 0 o t h e r w i s e Post Schmitt trigger 1 1 0 HSYNC(7) XOR Ref_Pol 1 1 1 Fosc Osc_Div
5
Func_Sel
6 7
EnPLS EnDLS
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ICS1523
Name: Register: Index: Loop Control Register 1h Read / Write*
Bit Name Bit # Reset Value Description
PFD0-2 Reserved PSD 0-1 Reserved 0-2 3 4-5 6-7 0 0 0 0 Phase Frequency Detector Gain Reserved Post-Scaler Divider Reserved
Bit
0-2
Name
PFD0-2
Description
Phase/Frequency Detector Gain
Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 PFD Ga i n ( A/ 2 r a d) 1 2 4 8 16 32 64 128
3 4-5
Reserved PSD 0-1 Post-Scaler Divider Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5 0 0 1 1 Bit 4 0 1 0 1 PSD Divider 2 (default) 4 8 16
6-7
Reserved
* Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
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ICS1523
Name: Register: Index: Feedback Divider 0 Register / Feedback Divider 1 Register 2h, 3h Read / Write*
Bit Name
FBD 0-7
Index
2
Bit #
0 -7
Reset Value
FF
Description
PLL Feedback Divider LSBs (0 -7).* When Bit 0 = 0, then the total number of pixels is even. When Bit 0 = 1, then the total number of pixels is odd. PLL Feedback Divider MSBs (8 -11)*
FBD 8 -11 Reserved
3 3
0 -3 4 -7
F
Reserved
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS 1523 generates between HSYNCs. Program these registers with the total number of horizontal pixels per line minus 8.
Reg 3 21 Reg 2 43
Feedback Divider Modulus
=
3
0
7
6
5
2
1
0
+8
12 Feedback Divider Modulus 4103
* Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
Name: Register: Index:
DPA Offset Register 4h Read / Write
Bit Name
DPA_OS0-5 Reserved Fil_Sel
Bit # Reset Value
0-5 6 7 0 0 0
Description
Dynamic Phase Adjust Offset Reserved Loop Filter Select
Bit
0-5
Name
DPA_OS0-5
Description
Dynamic Phase Adjust Offset. Selects clock edge offset in discrete steps from zero to one clock period minus one step. Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1). Note: Offsets equal to or greater than one clock period are neither recommended nor supported. Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps. Selects external loop filter (0) or internal loop filter (1). The use of an external loop filter is strongly recommended for all designs. Suggested component values are available from the ICS1523 Demo Board Guide (1523DB.pdf) or the ICS1523 Register Tool (inst1523.exe) available on our web site at: (http://www.icst.com/products/pinfo/1523.htm).
7
Fil_Sel
10
ICS1523
Name: Register: Index: DPA Control Register 5h Read / Write*
Bit Name
DPA_Res 0-1 Metal_Rev
Bit # Reset Value
0-1 2- 7 3 0
Description
Dynamic Phase Adjust Resolution Select. Metal Mask Revision Number.
Bit
0-1
Name
DPA_Res 0 -1
Description
Dynamic Phase Adjust (DPA) Resolution Select. It is not recommended to use the DPA above 160 MHz.
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Delay Elements 16 32 Reserved 64 12
CLK Range, MHz 48 24 80 40
160
2-7
Metal_Rev
Metal Mask Revision Number. After power-up, register bits 7:2 must be written with 111111. After this write, a read indicates the metal mask revision, as below.
Revision A B C1 C2 D E F G Bit 7 1 0 1 0 1 1 1 1 Bit 6 1 1 0 0 1 1 1 1 Bit 5 1 1 1 1 0 1 1 1 Bit 4 1 1 1 1 1 0 1 1 Bit 3 1 1 1 1 1 1 0 1 Bit 2 1 1 1 1 1 1 1 0
* Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
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ICS1523
Name: Register: Index: Output Enable Register 6h Read / Write
Bit Name Bit # Reset Value Description
OE_Pck OE_Tck OE_P2 OE_T2 OE_F Ck2_Inv Out_Scl 0 1 2 3 4 5 6-7 0 0 0 0 0 0 0 Output Enable for CLK Outputs (PECL) Output Enable for CLK Output (SSTL_3) Output Enable for CLK/2 Outputs (PECL) Output Enable for CLK2 Output (SSTL_3) Output Enable for FUNC Output (SSTL_3) CLK/2 Invert CLK Scaler
Bit
0
Name
OE_Pck
Description
Output Enable for CLK Outputs (PECL) 0 = High Z 1 = Enabled Output Enable for CLK Output (SSTL_3) 0 = High Z 1 = Enabled Output Enable for CLK/2 Outputs (PECL) 0 = High Z 1 = Enabled Output Enable for CLK/2 Output (SSTL_3) 0 = High Z 1 = Enabled Output Enable for FUNC Output (SSTL_3) 0 = High Z 1 = Enabled CLK/2 Invert 0 = Not Inverted 1 = Inverted Clock (CLK) Scaler
Bit 7 0 0 1 1 Bit 6 0 1 0 1 CLK Divider 1 2 4 8
1
OE_Tck
2
OE_P2
3
OE_T2
4
OE_F
5
Ck2_Inv
6 -7
Out_Scl
12
ICS1523
Name: Register: Index: Oscillator Divider Register 7h Read / Write
Bit Name
Osc_Div 0-6 In_Sel
Bit #
0-6 7
Reset Value
0 1
Description
Osc Divider Modulus Input Select
Bit
0-6
Name
Osc_Div 0-6
Description
Oscillator Divider Modulus. Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. Input Select Selects the input to the Phase/Frequency Detector 0 = HSYNC 1 = Osc Divider
7
In_Sel
Name: Register: Index:
RESET Register 8h Write
Bit Name
DPA Reset PLL Reset
Bit #
0 -3 4 -7
Reset Value
x x
Description
Writing xAh to this register resets DPA working register 5 Writing 5xh to this register resets PLL working registers 1-3
Bit
0 -3 4 -7
Name
DPA PLL
Description
Writing xAh to this register resets DPA working register 5 Writing 5xh to this register resets PLL working registers 1-3
Value xA 5x 5A
Resets DPA PLL DPA and PLL
13
ICS1523
Name: Register: Index: Chip Version Register 10 h Read
Bit Name
Chip Ver
Bit #
0-7
Reset Value
17
Description
Chip Version 23 (17h )
Name: Register: Index:
Chip Revision Register 11h Read
Bit Name
Chip Rev
Bit #
0 -7
Reset Value
01+
Description
Initial value 01h. +Value increments with each all-layer change.
Name: Register: Index:
Status Register 12 h Read
Bit Name
DPA_Lock PLL_Lock Reserved
Bit # Reset Value
0 1 2 -7 N/A N/A 0
Description
DPA Lock Status PLL Lock Status Reserved
Bit
0
Name
DPA_Lock
Description
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked PLL Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked
1
PLL_Lock
2 -7
Reserved
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ICS1523
ICS1523 Software Programming Flow
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ICS1523
I2C Data Characteristics
Bit transfer on the I2C-bus
START and STOP conditions
Acknowledge on the I2C-bus
These waveforms are from "The I 2 C-bus and how to use it," published by Philips Semiconductor. The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf
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ICS1523
I2C Data Format
RANDOM REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 x WA 7 bit address START condition A AP
register address Acknowledge WRITE command
data Acknowledge
STOP condition Acknowledge
RANDOM REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition AS0 1 0 0 1 1XRA 7 bit address data Repeat START Acknowledge Acknowledge READ command AP STOP condition NO Acknowledge
register address Acknowledge WRITE command
SEQUENTIAL REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition A A A AP Acknowledge Acknowledge STOP condition
register address Acknowledge WRITE command
data Acknowledge
data Acknowledge
SEQUENTIAL REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 bit address START condition AS0 1 0 0 1 1XRA 7 bit address data Repeat START Acknowledge Acknowledge READ command A AP data NO Acknowledge Acknowledge STOP condition
register address Acknowledge WRITE command
Direction:
From bus host to device
From device to bus host
Note: 1. 2. 3. All values are transmitted with the most-significant bit first and the least-significant bit last. The value of the X bit equals the logic state of pin 13 (I2CADR). R = READ = 1 and W = WRITE = 0
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ICS1523
ICS1523 Video Mode Reference Table
The use of an external loop filter is strongly recommended in All Designs. The ICS1523 Video Mode Reference Table (previously included in this data sheet) lists information on the various video modes that can be used with the ICS1523. To reference this table, see the ICS1523 Demo Board Guide (1523DB.pdf) available on our web site at: (http://www.icst.com) under the ICS1523 area.
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ICS1523
General Layout Guidelines
Use a PC board with at least four layers: one power, one ground, and two signal. No special cutouts are required for power and ground planes. All supply voltages must be supplied from a common source and must ramp up together. Flux and other board surface debris can degrade the performance of the external loop filter. Ensure that the 1523 area of the board is free of contaminants.
5. PECL Outputs Implement these outputs as
microstrip transmission lines. The trace widths shown are for 75 W characteristic impedance, presuming .067 in. between layers. Locate the optional series snubbing resistors as close as possible to the pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes.
Specific Layout Guidelines
1. Digital Supply (VDD) Bypass pin 1 (VDD) to pin 2
(VSS) with 4.7-F and 0.1-F capacitors, located as close as possible to the pins. Traces must be maximally wide and include multiple surface-etched vias to the appropriate plane. ter is strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9 (EXTFIL and EXTFILRET) as possible. Typical loop filter values are 6.8K W for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.). (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7-F and 0.1-F capacitors. Bypass pin 10 to pin 11 (VSSA) with a 0.1-F capacitor. Locate these components as close as possible to the pins. Traces must be maximally wide and have multiple surface-etched vias to the power or ground planes. .
[These termination resistors are omitted if the load device implements them internally. For details, see the ICS application note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing a Custom Interface for the ICS1523 (1523AN4.)]
6. Output Driver Supply Bypass pin 18 (VDDQ) to pin
2. External Loop Filter The use of an external loop fil-
19 (VSSQ) with 4.7-F and 0.1-F capacitors, located as close as possible to the pins. Traces must be maximally wide and include multiple surface-etched vias to the appropriate plane. conventional CMOS rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, PECL Outputs apply. See JEDEC documents JESD8-A and JESD8-8.
7. SSTL_3 Outputs SSTL_3 outputs can be used like
3. Analog PLL Supply (VDDA) Decouple pin 10
4 1
1
set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1-F capacitor.
ICS1523
4. PECL Current Set Resistor Locate PECL current-
5 6 7
2 3
Note: Drawing is not to scale. It is for illustrative purposes only.
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ICS1523
Power Supply Considerations
The ICS1523 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1523, the supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms should be sufficient.
SSTL_3 Outputs
Unterminated Outputs
In the ICS1523, unterminated SSTL output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these singleended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz. SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1523 SSTL outputs are only slightly improved by termination in a low impedance. The ICS1523 SSTL output source impedance is typically less than 60W. Termination impedance of 100W reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
Terminated Outputs
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ICS1523
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . 4.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS 0.3V to 5.5 V Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA 0.3 V to VDDA +0.3 V Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ 0.3 V to VDDQ +0.3 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175C Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV (*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
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ICS1523
Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . . 3.0 to 3.6 V Operating Temperature (Ambient) . . . . . . . . . 0 to +70C
D C S u p p l y C u r re n t
PA R A M E T E R Supply Current, Digital Supply Current, Output Drivers Supply Current, Analog PA R A M E T E R Input High Voltage Input Low Voltage Input Hysteresis Input High Current Input Low Current Input Capacitance PA R A M E T E R Output Low Voltage IIH IIL Cin SYMBOL VOL CONDITIONS IOUT = 3 mA. VOH = 6.0V maximum as determined by the external pull-up resistor. CONDITIONS IOUT = 0 MIN -- VIH = VDD VIL = 0 SYMBOL IDDD IDDQ I D DA SYMBOL VIH VIL CONDITIONS VDDD = 3.6V VDDQ = 3.6V, no output drivers enabled. VDDA = 3.6V MIN -- -- -- MAX 25 6 5 MAX 5.5 0.8 0.6 10 200 10 MAX 0.4 UNITS mA mA mA UNITS V V V A A pF UNITS V
D i g i t a l I n p u t s ( S DA , S C L , P D E N , E X T F B , H S Y N C , O S C ,
I 2C A D R )
MIN 2 VSS-0.3 0.2 -- -- -- MIN
CONDITIONS
S DA ( I n O u t p u t M o d e : S DA i s B i d i re c t i o n a l )
PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)
PA R A M E T E R Output High Voltage Output Low Voltage (Note: VOL must not fall below the level given so that the correct value for IOUT can be maintained.) PA R A M E T E R Output Resistance SYMBOL VOH MAX VDD UNITS V
VOL
IOUT = programmed value
1.0
--
V
SSTL-3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
SYMBOL RO SYMBOL fHSYNC fOSC Reg 7:7 = 0 Reg 7:7 = 1 1 AC Input Characteristics
PA R A M E T E R HSYNC Input Frequency OSC Input Frequency
22
ICS1523
VCO Output Frequency and Intrinsic Jitter
700 700
600 Frequency (Slow: 3.0V @ 70C) Frequency (Nominal: 3.3V @ 30C) 500 VCO Frequency (MHz) Frequency (Fast: 3.6V @ 0C) Jitter (3.0V @ 70C) Jitter (3.3V @ 30C) Jitter (3.6V @ 0C) 400
600
500
400
Frequency 300 300
200 Jitter 100
200 Jitter (ps)
100
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VCO Voltage 2 2.2 2.4 2.6 2.8 3 3.2
0
23
ICS1523
DPA Delay-16 Element Resolution
20 18 16 14 12 10 8 6 4 2 0 0
50 MHz - SVGA @ 72 Hz 157.5 MHz - SXGA @ 85 Hz
ns Delay
4
8
12
16
DPA Setting
DPA Delay - 32 Element Resolution
45 40 35
25.175 MHz - VGA @ 60 Hz 78.75 MHz - XGA @ 75 Hz
ns Delay
30 25 20 15 10 5 0 0
4
8
12
16
20
24
28
32
DPA Setting DPA Delay - 64 Element Resolution
90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
12.27 MHz - NTSC 39.8 MHz - SVGA @ 60
ns Delay
64
Note: Maximum number of data points used for this graph.
DPA Setting
24
AC Timing Characteristics Overview
25 * Timing when Register 2, Bit 0 = 0 (Total number of pixels is even.) ** Timing when Register 2, Bit 0 = 1 (Total number of pixels is odd.)
ICS1523
ICS1523
Output Timing Diagram
Typical Transition Times*
Symbol tR tP tS tF REF PECL CLK SSTL-CLK FUNC_OUT Timing Description Rise 2.8 1.0 1.6 1.2 Fall 1.8 1.2 0.7 1.0 Units ns ns ns ns
Output Timing*
Symbol t0 t1 t2, t3 t4 t5 t6 t7 t8, t9 Timing Description HSYNC to REF delay REF to PECL clock delay PECL clock duty cycle PECL clock to SSTL_3 clock delay PECL clock to FUNC_OUT delay PECL clock to PECL/2 clock PECL clock to SSTL_3-CLK/2 delay SSTL clock duty cycle Mi n 11.3 -1.0 45 0.2 1.5 1.0 1.1 45 Typ 11.5 0.8 50 0.75 1.9 1.3 1.4 50 Max Units 12 2.2 55 1.2 2.3 1.5 1.8 55 ns ns % ns ns ns ns %
*Note: Measured at 3.6V 0C, 135-MHz output frequency, PECL clock lines to 75W termination, SSTL_3 clock lines unterminated, 20-pF load. Transition times vary based on termination.
26
ICS1523
24-Pin SOIC (wide body)
Ordering Information
ICS1523M
27
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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